View NJW1111_4131459.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJW1111
9-IN 3-OUT STEREO AUDIO SELECTOR
! GENERAL DESCRIPTION The NJW1111 is a 9-input 3-output stereo audio selector. It includes three independent 9input-1output stereo audio selectors and adjustable gain buffers. The NJW1111 performs superior audio characteristics such as low distortion, low output noise and low crosstalk. All of internal status and variables are controlled by three-wired serial bus. Selectable two Chip address is available for using two chips on same serial bus line. It is suitable for AV amplifier and receiver system and others. ! FEATURES * Operating Voltage * 9-Input, 3-Output Stereo Audio Selector * Operating Current * Low Distortion * Low Output Noise * Low Crosstalk * Channel Separation * Variable Gain Buffer * 3-Wired Serial Control * Bi-CMOS Technology * Package Outline ! BLOCK DIAGRAM
InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 ADR V+ V+
! PACKAGE OUTLINE
NJW1111V
4.5 to 7.5V 8mA typ. 0.0007% typ. -116dBV typ. 110dB typ. 110dB typ. 0, 3 to 8dB/0.5dB step
SSOP32
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
+
100F
100F
32
31
30
29
28
27
26
25
24
23
GND
22
21
20
19
18
17
Gain
50KX 8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Control Logic
GND
1
10F
+
2
10F
+
3
10F
+
4
10F
+
5
10F
+
6
10F
+
7
10F
+
8
10F
+
9
10F
+
10
10F
11
+
12
10F
+
13
10F
+
14
15
16
InA1
InA2
InA3
InA4
InA5
InA6
InA7
InA8
InA9
OutA1
OutA2
OutA3
LATCH
DATA
CLOCK
Ver.4.0
-1-
NJW1111
!PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 GND OutA1 OutA2 OutA3 LATCH DATA CLOCK
InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9
32 31 30 29 28 27 26 25 24
GND 23 OutB1 22 OutB2 21 OutB3 20 ADR V+ V19 16 18 17
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol
InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 GND OutA1 OutA2 OutA3 LATCH DATA CLOCK
Function
Ach Input 1 Ach Input 2 Ach Input 3 Ach Input 4 Ach Input 5 Ach Input 6 Ach Input 7 Ach Input 8 Ach Input 9 Ground Terminal Ach Output 1 Ach Output 2 Ach Output 3 LATCH DATA CLOCK
No.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Symbol
VV+ ADR OutB3 OutB2 OutB1 GND InB9 InB8 InB7 InB6 InB5 InB4 InB3 InB2 InB1
Function
V- Power Supply Terminal V+ Power Supply Terminal Chip address setting terminal Bch Output 3 Bch Output 2 Bch Output 1 Ground Terminal Bch Input 9 Bch Input 8 Bch Input 7 Bch Input 6 Bch Input 5 Bch Input 4 Bch Input 3 Bch Input 2 Bch Input 1
-2-
Ver.4.0
NJW1111
! ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER SYMBOL
Power Supply Voltage Maximum Input Voltage Power Dissipation Operating Temperature Range Storage Temperature Range V
+
RATING +8/-8
V /V 800
+ -
UNIT
V V mW C C
VIM PD Topr Tstg
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
-40 to +85 -40 to +125
! RECOMMENDED OPERATING CONDITIONS (Ta=25C)
PARAMETER Operating Voltage SYMBOL V /V
+ -
TEST CONDITION
MIN.
TYP.
MAX.
UNIT V
-
4.5
7.0
7.5
! ELECTRICAL CHARACTERISTICS +Power Supply (Ta=25C, V /V =7V)
PARAMETER Supply Current 1 Supply Current 2 SYMBOL ICC IEE
+
+
TEST CONDITION V , No Signal V No Signal
-
MIN. 4.0 4.0
TYP. 8.0 8.0
MAX. 12.0 12.0
UNIT MA MA
AC CHARACTERISTICS (Ta=25C, V /V =7V, VIN=1Vrms,f=1kHz,RL=47k)
PARAMETER Maximum Output Voltage Voltage Gain 1 Voltage Gain 2 Total Harmonic Distortion 1 Total Harmonic Distortion 2 Total Harmonic Distortion 3 Mute Level Output Noise Cross Talk 1 Cross Talk 2 Channel Separation 1 Channel Separation 2 SYMBOL VOM GV1 GV2 THD1 THD2 THD3 ATT VNO CT1 CT2 CS1 CS2 TEST CONDITION THD=1% VIN=200mVrms, Gain=6dB BW=400Hz-30kHz Vin=2Vrms, BW=400Hz-30kHz f=10kHz, BW=400Hz-30kHz Selector=Mute, A-weighted Rg=0, A-Weighted Rg=0, A-Weighted Rg=0, f=20kHz Rg=0, A-Weighted Rg=0, f=20kHz
+ -
MIN. 10.6
(3.4)
TYP. 12.9
(4.4)
MAX. 0.5
UNIT dBV
(Vrms)
-0.5 5.0 -
0 6.0 0.0007 0.001 0.001 -110 -116
(1.6)
dB 7.0 0.02 -106
(5.0)
%
dB dBV
(Vrms)
-110 -96 -110 -96
dB -90 dB BW: Band Width
Logic Control Characteristics (Ta=25C, V /V =7V)
PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VADRH VADRL TEST CONDITION ADR Terminal ADR Terminal MIN. 2.5 0 TYP. MAX. V
+
UNIT
V 1.5
Ver.4.0
-3-
NJW1111
! TERMINAL DESCRIPTION
PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE
V+
1 to 9 32 to 24
InA1 to 9 InB1 to 9
Ach Input 1 to 9 Bch Input 1 to 9
200 50k V-(sub)
V+
0V
GND
V+ 50
11 to 13 22 to 20
OutA1 to 3 OutB1 to 3
Ach Output 1 to 3 Bch Output 1 to 3
0V
50 200 V-(sub)
18
V
+
V+ Power Supply Terminal
V+
V-(sub)
V+
10 23
GND
Ground Terminal
0V
V-(sub)
V+
14 15 16 19
LATCH DATA CLOCK ADR
LATCH DATA CLOCK Chip address setting terminal
4k
0V
8k V-(sub)
-4-
Ver.4.0
NJW1111
! CONTROL DATA FORMAT
t7 t1 t2 t3 t4 t8
LATCH
CLOCK
MSB LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA
D15
()
MSB First
t5 t6
SYMBOL
t1 t2 t3 t4 t5 t6 t7 t8
PARAMETER CLOCK Clock Width CLOCK Pulse Width (High) CLOCK Pulse Width (Low) LATCH Rise Hold Time DATA Setup Time DATA Hold Time CLOCK Setup Time LATCH High Pulse Width
MIN
4 2 2 4 1.6 1.6 1.6 1.6
TYP
-
MAX
-
UNIT
sec sec sec sec sec sec sec sec
Ver.4.0
-5-
NJW1111
! CONTROL DATA NJW1111 control data is constructed with 16bits.
MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Setting DATA
Select Address
Chip Address
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 0 D6 0 0 0 D5 0 0 1 D4 0 1 0 D3 * * * D2 * * * D1 * * * D0 * * *
Gain1 Gain2 Gain3
Selector1 Selector2 Selector3
* Chip address is set by chip address select terminal (ADR) status.
Chip address select terminal
Low High D3 1 1
Chip Address D2 0 0 D1 1 1 D0 0 1
!INITIAL CONDITION
MSB
D15 0 0 0 D14 0 0 0 D13 0 0 0 D12 0 0 0 D11 0 0 0 D10 0 0 0 D9 0 0 0 D8 0 0 0 D7 0 0 0 D6 0 0 0 D5 0 0 1 D4 0 1 0 D3 * * * D2 * * * D1 * * * D0 * * *
* Chip address is set by chip address select terminal (ADR) status.
-6-
Ver.4.0
NJW1111
! CONTROL DATA
D15
D14
D13
D12
D11
D10
D9
D8
D7 0 0 0
D6 0 0 0
D5 0 0 1
D4 0 1 0
D3 * * *
D2 * * *
D1 * * *
D0 * * *
Gain1 Gain2 Gain3
Selector1 Selector2 Selector3
a)Gain
DATA Setting
D15 0 0 0 0 0 0 0 0 1 1 1 1 D14 0 0 0 0 1 1 1 1 0 0 0 0 D13 0 0 1 1 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 0 1 0 1 0dB +3.0 dB +3.5 dB +4.0 dB +4.5 dB +5.0 dB +5.5 dB +6.0 dB +6.5 dB +7.0 dB +7.5 dB +8.0 dB
b)Input Selector
DATA Setting
D11 0 0 0 0 0 0 0 0 1 1 D10 0 0 0 0 1 1 1 1 0 0 D9 0 0 1 1 0 0 1 1 0 0 D8 0 1 0 1 0 1 0 1 0 1 Mute() InA1/B1 InA2/B2 InA3/B3 InA4/B4 InA5/B5 InA6/B6 InA7/B7 InA8/B8 InA9/B9
Ver.4.0
-7-
NJW1111
! APPLICATION CIRCUIT
InB1
InB2
InB3
InB4
InB5
InB6
InB7
InB8
InB9
OutB1
OutB2
OutB3
ADR
V+
V+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10F
+
10 F
+
10F
+
10F
+
+
100F
100F
32
31
30
29
28
27
26
25
24
23
GND
22
21
20
19
18
17
Gain
50KX 8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Gain
8dB to 3dB / 0.5dBstep
Control Logic
GND
1
10F
+
2
10F
+
3
10F
+
4
10F
+
5
10F
+
6
10F
+
7
10F
+
8
10F
+
9
10F
+
10
10 F
11
+
12
10F
+
13
10F
+
14
15
16
InA1
InA2
InA3
InA4
InA5
InA6
InA7
InA8
InA9
OutA1
OutA2
OutA3
LATCH
DATA
CLOCK
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
-8-
Ver.4.0

▲Up To Search▲

Price & Availability of NJW1111

	To Download NJW1111 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .